interAptiv | SystemC TLM Models

Model Information

This page provides detailed information about the SystemC TLM2 Fast Processor Model of the MIPS interAptiv core.
Processor IP owner is MIPS.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Embedded Software Development tools
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Overview of MIPS interAptiv Fast Processor Model
Model Variant name: interAptiv
Description:
    MIPS32 Configurable Processor Model
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    only MIPS32 Instruction set implemented
    MMU Type: Standard TLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Segmentation control implemented
    Enhanced virtual address (EVA) supported
    Vectored interrupts implemented
    MIPS16e ASE implemented
    MT ASE implemented
    DSP ASE Rev 2 implemented

Model downloadable (needs registration and to be logged in) in package mips32.model for Windows32 and for Linux32. Note that the Model is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant interAptiv is available OVP_Model_Specific_Information_mips32_r1r5_interAptiv.pdf.

Configuration
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips32_r1r5/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port Type	Name	Width (bits)	Description
master	INSTRUCTION	12
master	DATA	12

SystemC Signal Ports (Net Ports)

Port Type	Name	Description
reset	input
dint	input
int0	input
int1	input
int2	input
int3	input
int4	input
int5	input
int6	input
int7	input
int8	input
int9	input
int10	input
int11	input
int12	input
int13	input
int14	input
int15	input
int16	input
int17	input
int18	input
int19	input
int20	input
int21	input
int22	input
int23	input
int24	input
int25	input
int26	input
int27	input
int28	input
int29	input
int30	input
int31	input
int32	input
int33	input
int34	input
int35	input
int36	input
int37	input
int38	input
int39	input
yq_CPU0	input
yq0_CPU0	input
yq1_CPU0	input
yq2_CPU0	input
yq3_CPU0	input
yq4_CPU0	input
yq5_CPU0	input
yq6_CPU0	input
yq7_CPU0	input
yq8_CPU0	input
yq9_CPU0	input
yq10_CPU0	input
yq11_CPU0	input
yq12_CPU0	input
yq13_CPU0	input
yq14_CPU0	input
yq15_CPU0	input
hwint0_CPU0_VPE0	input
hwint1_CPU0_VPE0	input
hwint2_CPU0_VPE0	input
hwint3_CPU0_VPE0	input
hwint4_CPU0_VPE0	input
hwint5_CPU0_VPE0	input
nmi_CPU0_VPE0	input
hwint0	input
vc_run_CPU0_VPE0	input
hwint0_CPU0_VPE1	input
hwint1_CPU0_VPE1	input
hwint2_CPU0_VPE1	input
hwint3_CPU0_VPE1	input
hwint4_CPU0_VPE1	input
hwint5_CPU0_VPE1	input
nmi_CPU0_VPE1	input
vc_run_CPU0_VPE1	input
yq_CPU1	input
yq0_CPU1	input
yq1_CPU1	input
yq2_CPU1	input
yq3_CPU1	input
yq4_CPU1	input
yq5_CPU1	input
yq6_CPU1	input
yq7_CPU1	input
yq8_CPU1	input
yq9_CPU1	input
yq10_CPU1	input
yq11_CPU1	input
yq12_CPU1	input
yq13_CPU1	input
yq14_CPU1	input
yq15_CPU1	input
hwint0_CPU1_VPE0	input
hwint1_CPU1_VPE0	input
hwint2_CPU1_VPE0	input
hwint3_CPU1_VPE0	input
hwint4_CPU1_VPE0	input
hwint5_CPU1_VPE0	input
nmi_CPU1_VPE0	input
vc_run_CPU1_VPE0	input
hwint0_CPU1_VPE1	input
hwint1_CPU1_VPE1	input
hwint2_CPU1_VPE1	input
hwint3_CPU1_VPE1	input
hwint4_CPU1_VPE1	input
hwint5_CPU1_VPE1	input
nmi_CPU1_VPE1	input
vc_run_CPU1_VPE1	input
yq_CPU2	input
yq0_CPU2	input
yq1_CPU2	input
yq2_CPU2	input
yq3_CPU2	input
yq4_CPU2	input
yq5_CPU2	input
yq6_CPU2	input
yq7_CPU2	input
yq8_CPU2	input
yq9_CPU2	input
yq10_CPU2	input
yq11_CPU2	input
yq12_CPU2	input
yq13_CPU2	input
yq14_CPU2	input
yq15_CPU2	input
hwint0_CPU2_VPE0	input
hwint1_CPU2_VPE0	input
hwint2_CPU2_VPE0	input
hwint3_CPU2_VPE0	input
hwint4_CPU2_VPE0	input
hwint5_CPU2_VPE0	input
nmi_CPU2_VPE0	input
vc_run_CPU2_VPE0	input
hwint0_CPU2_VPE1	input
hwint1_CPU2_VPE1	input
hwint2_CPU2_VPE1	input
hwint3_CPU2_VPE1	input
hwint4_CPU2_VPE1	input
hwint5_CPU2_VPE1	input
nmi_CPU2_VPE1	input
vc_run_CPU2_VPE1	input
yq_CPU3	input
yq0_CPU3	input
yq1_CPU3	input
yq2_CPU3	input
yq3_CPU3	input
yq4_CPU3	input
yq5_CPU3	input
yq6_CPU3	input
yq7_CPU3	input
yq8_CPU3	input
yq9_CPU3	input
yq10_CPU3	input
yq11_CPU3	input
yq12_CPU3	input
yq13_CPU3	input
yq14_CPU3	input
yq15_CPU3	input
hwint0_CPU3_VPE0	input
hwint1_CPU3_VPE0	input
hwint2_CPU3_VPE0	input
hwint3_CPU3_VPE0	input
hwint4_CPU3_VPE0	input
hwint5_CPU3_VPE0	input
nmi_CPU3_VPE0	input
vc_run_CPU3_VPE0	input
hwint0_CPU3_VPE1	input
hwint1_CPU3_VPE1	input
hwint2_CPU3_VPE1	input
hwint3_CPU3_VPE1	input
hwint4_CPU3_VPE1	input
hwint5_CPU3_VPE1	input
nmi_CPU3_VPE1	input
vc_run_CPU3_VPE1	input

No FIFO Ports in interAptiv.

Exceptions

Name	Code	Description
Int	0
Mod	1
TLBL	2
TLBS	3
AdEL	4
AdES	5
IBE	6
DBE	7
Sys	8
Bp	9
RI	10
CpU	11
Ov	12
Tr	13
FPE	15
Impl1	16
Impl2	17
C2E	18
TLBRI	19
TLBXI	20
MDMX	22
WATCH	23
MCheck	24
Thread	25
DSPDis	26
Prot	29
CacheErr	30

Execution Modes

Mode	Code	Description
KERNEL	0
DEBUG	1
SUPERVISOR	2
USER	3

More Detailed Information

The interAptiv SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips32_r1r5_interAptiv.pdf.

Other Sites/Pages with similar information

Information on the interAptiv OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: Debugging with Imperas eGui running on OVP platforms
http://www.ovpworld.org: Function by function Reference Guide for BHM / PPM APIs.

Two Videos on these models (from other sites)
http://www.ovpworld.org: ARC Demo Video Presentation
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation

Currently available Fast Processor Model Families.

Family	Model Variant
RISC-V Models	RISC-V Models aliases RV32I RV32IM RV32IMC RV32IMAC RV32G RV32GC RV32GCN RV32E RV32EC RV64I RV64IM RV64IMC RV64IMAC RV64G RV64GC RV64GCN (aliases)
MIPS Models	MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP microAptivCF interAptiv interAptivUP proAptiv 5Kf 5Kc 5KEf 5KEc M5100 M5150 M6200 M6250 MIPS32R6 P5600 P6600 I6400 MIPS64R6 I6500 (aliases)
ARM Models	ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 Cortex-A17MPx1 Cortex-A17MPx2 Cortex-A17MPx3 Cortex-A17MPx4 AArch32 AArch64 Cortex-A32MPx1 Cortex-A32MPx2 Cortex-A32MPx3 Cortex-A32MPx4 Cortex-A35MPx1 Cortex-A35MPx2 Cortex-A35MPx3 Cortex-A35MPx4 Cortex-A53MPx1 Cortex-A53MPx2 Cortex-A53MPx3 Cortex-A53MPx4 Cortex-A55MPx1 Cortex-A55MPx2 Cortex-A55MPx3 Cortex-A55MPx4 Cortex-A57MPx1 Cortex-A57MPx2 Cortex-A57MPx3 Cortex-A57MPx4 Cortex-A72MPx1 Cortex-A72MPx2 Cortex-A72MPx3 Cortex-A72MPx4 Cortex-A73MPx1 Cortex-A73MPx2 Cortex-A73MPx3 Cortex-A73MPx4 Cortex-A75MPx1 Cortex-A75MPx2 Cortex-A75MPx3 Cortex-A75MPx4 MultiCluster ARMv6-M ARMv7-M Cortex-M0 Cortex-M0plus Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
POWER Models	POWER Models aliases mpc82x UISA m476 m470 m460 m440 (aliases)
Renesas Models	Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R RH850G3M m16c r8c RL78-S1 RL78-S2 RL78-S3 (aliases)
Other Models	Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Andes_N25 Andes_NX25 Microsemi_CoreRISCV Microsemi_MiV_RV32IMA SiFive_E31 SiFive_E51 SiFive_U54 Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_V9_50 Xilinx MicroBlaze_V10_00 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)